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ispLSI 2096VE
3.3V In-System Programmable SuperFASTTM High Density PLD Features
* SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC -- 4000 PLD Gates -- 96 I/O Pins, Six Dedicated Inputs -- 96 Registers -- High Speed Global Interconnect -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic -- 100% Functional, JEDEC and Pinout Compatible with ispLSI 2096V Devices -- Pinout Compatible with ispLSI 2192VE * 3.3V LOW VOLTAGE 2096 ARCHITECTURE -- Interfaces with Standard 5V TTL Devices * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 250MHz* Maximum Operating Frequency -- tpd = 4.0ns* Propagation Delay -- Electrically Erasable and Reprogrammable -- Non-Volatile -- 100% Tested at Time of Manufacture -- Unused Product Term Shutdown Saves Power * IN-SYSTEM PROGRAMMABLE -- 3.3V In-System Programmability (ISPTM) Using Boundary Scan Test Access Port (TAP) -- Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality -- Reprogram Soldered Devices for Faster Prototyping * 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE * THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS -- Enhanced Pin Locking Capability -- Three Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Programmable Output Slew Rate Control -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity * ispDesignEXPERTTM - LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING -- Superior Quality of Results -- Tightly Integrated with Leading CAE Vendor Tools -- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM -- PC and UNIX Platforms
*Advanced Information
(R)
Functional Block Diagram
Output Routing Pool (ORP) Output Routing Pool (ORP)
C7 A0
C6
C5
C4
C3
C2
C1
C0 B7
Output Routing Pool (ORP)
DQ
A1
A2
GLB
Logic Array
DQ
B6
DQ
Global Routing Pool (GRP)
B5
DQ
A3 A4 A5 A6 A7 B0 B1 B2 B3
B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
0919/2096VE
Description
The ispLSI 2096VE is a High Density Programmable Logic Device containing 96 Registers, six Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2096VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2096VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2096VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. C7 (see Figure 1). There are a total of 24 GLBs in the ispLSI 2096VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. The devices also have 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can
Copyright (c) 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2096ve_05
1
Output Routing Pool (ORP)
Specifications ispLSI 2096VE
Functional Block Diagram
Figure 1. ispLSI 2096VE Functional Block Diagram
GOE 0 GOE 1 I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 IN 5 IN 4
Input Bus
Input Bus Output Routing Pool (ORP)
Megablock Generic Logic Blocks (GLBs) C7
Output Routing Pool (ORP)
C6
C5
C4
C3
C2
C1
C0
Output Routing Pool (ORP)
Input Bus
I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 TDI/IN 0 TMS/IN 1
Input Bus
I/O 4 I/O 5 I/O 6 I/O 7
A1
A2
Global Routing Pool (GRP)
Output Routing Pool (ORP)
I/O 0 I/O 1 I/O 2 I/O 3
A0
B7
I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48
B6
B5
A3
B4
A4
A5
A6
A7
B0
B1
B2
B3
Output Routing Pool (ORP)
RESET BSCAN
TDO/IN 2 TCK/IN 3 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31
Output Routing Pool (ORP)
Input Bus
CLK 0 CLK 1 CLK 2 I/O 44 I/O 45 I/O 46 I/O 47
Input Bus
I/O 32 I/O 33 I/O 34 I/O 35
I/O 36 I/O 37 I/O 38 I/O 39
I/O 40 I/O 41 I/O 42 I/O 43
0917/2096VE
be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 5V signal levels to support mixed-voltage systems. Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the two ORPs. Each ispLSI 2096VE device contains three Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2096VE device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock.
Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 2096VE are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools.
2
Y0 Y1 Y2
Specifications ispLSI 2096VE
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +5.4V Input Voltage Applied ............................... -0.5 to +5.6V Off-State Output Voltage Applied ............ -0.5 to +5.6V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial TA = 0C to + 70C TA = -40C to + 85C MIN. 3.0 3.0 VSS - 0.5 2.0 MAX. 3.6 3.6 0.8 5.25 UNITS V V V V
VCC VIL VIH
Table 2-0005/2096VE
Capacitance (TA=25C, f=1.0 MHz)
SYMBOL PARAMETER Dedicated Input Capacitance I/O Capacitance Clock and Global Output Enable Capacitance TYPICAL 8 6 10 UNITS pf pf pf TEST CONDITIONS VCC = 3.3V, VIN = 0.0V VCC = 3.3V, VI/O = 0.0V VCC = 3.3V, VY = 0.0V
Table 2-0006/2096VE
C1 C2 C3
Erase Reprogram Specifications
PARAMETER Erase/Reprogram Cycles MINIMUM 10000 MAXIMUM - UNITS Cycles
Table 2-0008/2096VE
3
Specifications ispLSI 2096VE
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V 1.5ns 10% to 90% 1.5V 1.5V See Figure 2
Table 2-0003/2096VE
Figure 2. Test Load
+ 3.3V R1 Device Output R2 CL* Test Point
Output Load Conditions (see Figure 2)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 316 316 316 R2 348 348 348 348 348 CL 35pF 35pF 35pF 5pF 5pF
*CL includes Test Fixture and Probe Capacitance.
0213A/2096VE
C
Table 2-0004/2096VE
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current BSCAN Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOL= 8 mA IOH = -4 mA 0V VIN VIL (Max.) (VCC - 0.2)V VIN VCC V VIN 5.25V CC 0V VIN VIL 0V VIN VIL VCC = 3.3V, VOUT = 0.5V VIL = 0.0V, VIH = 3.0V fCLOCK = 1 MHz CONDITION MIN. - 2.4 - - - - - - - TYP. - - - - - - - - 125
3
MAX. UNITS 0.4 - -10 10 10 -150 -150 -100 - V V A A A A A mA mA
VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4
Table 2-0007A/2096VE 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using six 16-bit counters. 3. Typical values are at VCC = 3.3V and TA= 25C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC .
4
Specifications ispLSI 2096VE
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST COND. A A A -- -- -- A -- -- A -- A -- B C B C -- --
3
# 1 2 3 4 5 6 7 8 9
DESCRIPTION
1
-250 -- -- 250
1 tsu2 + tco1
-200 -- -- 200 133 200 3.0 -- 0.0 4.0 -- 0.0 -- 4.0 -- -- -- -- 2.5 2.5 4.5 7.0 -- -- -- -- 3.5 -- -- 4.5 -- 6.0 -- 8.0 8.0 5.0 5.0 -- --
MIN. MAX. MIN. MAX. 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle GLB Reg. Setup Time before Clock, 4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock
2
Clock Frequency with External Feedback (
)
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low
ADVANCED INF ORMATION
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section.
Table 2-0030A/2096VE
5
Specifications ispLSI 2096VE
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST COND. A A A -- -- -- A -- -- A -- A -- B C B C -- --
3 1
# 1 2 3 4 5 6 7 8 9
DESCRIPTION
-135 -- --
2 1
-100 -- -- 100 77 100 6.5 -- 0.0 8.0 -- 0.0 -- 6.5 -- -- -- -- 5.0 5.0 10.0 13.0 -- -- -- -- 5.0 -- -- 6.0 -- 13.5 -- 15.0 15.0 9.0 9.0 -- --
MIN. MAX. MIN. MAX. 7.5 10.0 -- -- -- -- 4.0 -- -- 5.0 -- 10.0 -- 12.0 12.0 7.0 7.0 -- --
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle GLB Reg. Setup Time before Clock, 4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock Clock Frequency with External Feedback ( tsu2 + tco1)
135 100 143 5.0 -- 0.0 6.0 -- 0.0 -- 5.0 -- -- -- -- 3.5 3.5
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section.
Table 2-0030B/2096VE
6
Specifications ispLSI 2096VE
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER Inputs #
2
DESCRIPTION
-200
-135
-100
MIN. MAX. MIN. MAX. MIN. MAX. - - - - - - - - - 1.2 1.8 - - - - 1.0 - - - - - - - 1.2 1.4 - 0.5 1.1 0.6 1.4 1.9 2.9 2.9 2.9 0.0 - - 0.3 0.4 4.3 3.9 4.0 1.5 0.5 1.5 2.0 3.0 3.0 2.0 1.2 1.4 3.6 - - - - - - - - - 1.2 3.8 - - - - 1.6 - - - - - - - 1.6 1.8 - 0.5 1.7 1.2 3.7 3.7 4.7 4.7 4.7 0.5 - - 0.3 1.1 6.1 6.9 5.0 1.5 0.5 1.6 2.0 3.4 3.4 3.6 1.6 1.8 5.8 - - - - - - - - - 1.7 4.8 - - - - 2.6 - - - - - - - 2.4 2.6 - 0.7 2.5 1.8 5.2 4.7 6.2 6.2 6.2 1.0 - - 0.3 3.1 7.1 9.1 5.6 1.7 0.7 1.6 2.0 3.4 3.4 5.6 2.4 2.6 7.1
UNITS
tio tdin
GRP
20 Input Buffer Delay 21 Dedicated Input Delay 22 GRP Delay 23 4 Product Term Bypass Path Delay (Combinatorial) 24 4 Product Term Bypass Path Delay (Registered) 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 27 XOR Adjacent Path Delay
3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tgrp
GLB
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
ORP
28 GLB Register Bypass Delay 29 GLB Register Setup Time before Clock 30 GLB Register Hold Time after Clock 31 GLB Register Clock to Output Delay 32 GLB Register Reset to Output Delay 33 GLB Product Term Reset to Register Delay 34 GLB Product Term Output Enable to I/O Cell Delay 35 GLB Product Term Clock Delay 36 ORP Delay 37 ORP Bypass Delay 38 Output Buffer Delay 39 Output Slew Limited Delay Adder 40 I/O Cell OE to Output Enabled 41 I/O Cell OE to Output Disabled 42 Global Output Enable 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 45 Global Reset to GLB
torp torpbp
Outputs
tob tsl toen todis tgoe
Clocks
tgy0 tgy1/2
Global Reset
tgr
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036/2096VE
7
Specifications ispLSI 2096VE
ispLSI 2096VE Timing Model
I/O Cell GRP Feedback Ded. In Comb 4 PT Bypass #23 GRP #22 Reg 4 PT Bypass #24 20 PT XOR Delays #25, 26, 27 Reset #45 D RST #29, 30, 31, 32 GLB Reg Bypass #28 GLB Reg Delay Q ORP Bypass #37 ORP Delay #36 #38, 39 I/O Pin (Output) GLB ORP I/O Cell
#21 I/O Delay #20
I/O Pin (Input)
Control RE PTs OE #33, 34, CK 35 Y0,1,2 GOE 0 #43, 44 #42
#40, 41
0491/2032
Derivations of tsu, th and tco from the Product Term Clock tsu
= = = 3.1ns = = = = 2.9ns = = = = 8.4ns = Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.5 + 0.6 + 2.9) + (1.2) - (0.5 + 0.6 + 1.0) Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.5 + 0.6 + 4.0) + (1.8) - (0.5 + 0.6 + 2.9) Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.5 + 0.6 + 4.0) + (0.3) + (1.5 + 1.5)
th
tco
Note: Calculations are based on timing specifications for the ispLSI 2096VE-200L.
Table 2-0042/2096VE
8
Specifications ispLSI 2096VE
Power Consumption
Power consumption in the ispLSI 2096VE device depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax
240 ispLSI 2096VE 220 200
used. Figure 3 shows the relationship between power and operating speed.
ICC (mA)
180 160 140 120 0 50 100 150 200
fmax (MHz)
Notes: Configuration of six 16-bit counters Typical current at 3.3V, 25 C
ICC can be estimated for the ispLSI 2096VE using the following equation: ICC (mA) = 8.0 + (# of PTs * 0.63) + (# of Nets * Max Freq * 0.005) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127/2096VE
9
Specifications ispLSI 2096VE
Pin Description
NAME
I/O 0 - I/O 5 I/O 6 - I/O 11 I/O 12 - I/O 17 I/O 18 - I/O 23 I/O 24 - I/O 29 I/O 30 - I/O 35 I/O 36 - I/O 41 I/O 42 - I/O 47 I/O 48 - I/O 53 I/O 54 - I/O 59 I/O 60 - I/O 65 I/O 66 - I/O 71 I/O 72 - I/O 77 I/O 78 - I/O 83 I/O 84 - I/O 89 I/O 90 - I/O 95 GOE 0, GOE 1 IN 4, IN 5 BSCAN 21, 27, 35, 41, 51, 57, 64, 71, 85, 91, 99, 105, 115, 121, 128, 7, 80, 84, 19
TQFP PIN NUMBERS
22, 28, 36, 42, 52, 58, 65, 72, 86, 92, 100, 106, 116, 122, 1, 8, 17 113 23, 29, 37, 43, 53, 59, 67, 73, 87, 93, 101, 107, 117, 123, 3, 9, 24, 30, 38, 44, 54, 60, 68, 74, 88, 94, 102, 108, 118, 124, 4, 10, 25, 32, 39, 45, 55, 61, 69, 75, 89, 96, 103, 109, 119, 125, 5, 11, 26 33 40 46 56 62 70 76 90 97 104 110 120 126 6 12
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
Global Output Enables input pins. Dedicated input pins to the device. Input -- Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input -- This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin. Input -- This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. Output/Input -- This pin performs two functions. When BSCAN is logic low, it functions as an output pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. Input -- This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. Active Low (0) Reset pin which resets all of the registers in the device.
TDI/IN 0
20
TMS/IN 1
48
TDO/IN 2
112
TCK/IN 3
77
RESET Y0, Y1, Y2 GND VCC NC1
15 14 18, 111, 2, 95, 13, 83, 34, 127 16, 114 49, 78 50, 31, 82 63, 47, 79, 66, 98, 81,
Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. Ground (GND) VCC No Connect.
Table 2-0002-2096VE
1. NC pins are not to be connected to any active signal, VCC or GND.
10
Specifications ispLSI 2096VE
Pin Configuration
ispLSI 2096VE 128-Pin TQFP Pinout Diagram
I/O 84 GND I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 VCC IN 5 TDO/IN 2 GND I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 GND I/O 59 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
I/O 85 VCC I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 1NC Y0 RESET VCC GOE 1 GND BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 VCC I/O 10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ispLSI 2096VE
Top View
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
I/O 58 VCC I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 4 Y1 NC1 VCC GOE 0 GND Y2 TCK/IN 3 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 VCC I/O 37
1. NC pins are not to be connected to any active signals, VCC or GND.
I/O 11 GND I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 VCC TMS/IN 1 1NC GND I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 GND I/O 36
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
0124-2096VE
11
Specifications ispLSI 2096VE
Part Number Description ispLSI 2096VE - XX
Device Family Device Number Speed 250 = 250 MHz fmax* 200 = 200 MHz fmax 135 = 135 MHz fmax 100 = 100 MHz fmax
*Advanced information
X XXXX X
Grade Blank = Commercial I = Industrial Package T128 = 128-Pin TQFP Power L = Low
0212/2096VE
ispLSI 2096VE Ordering Information
COMMERCIAL
FAMILY fmax (MHz) 250 ispLSI 200 135 100 *Advanced information tpd (ns) 4.0 4.5 7.5 10 ORDERING NUMBER ispLSI 2096VE-250LT128* ispLSI 2096VE-200LT128 ispLSI 2096VE-135LT128 ispLSI 2096VE-100LT128 PACKAGE 128-Pin TQFP 128-Pin TQFP 128-Pin TQFP 128-Pin TQFP
Table 2-0041A/2096VE
INDUSTRIAL
FAMILY ispLSI fmax (MHz) 135 tpd (ns) 7.5 ORDERING NUMBER ispLSI 2096VE-135LT128I PACKAGE 128-Pin TQFP
Table 2-0041B/2096VE
12

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